This application claims the priority of German patent document 100 30 158.4, filed 20 Jun. 2000, the disclosure of which is expressly incorporated by reference herein.
The invention relates to an electronic control unit having a main microprocessor and a processor interface to a bus transceiver unit. Such a control unit is used, for example, in motor vehicles for transmission of motor-vehicle-related data via a data bus (for example, a CAN bus, German Patent Document DE 35 06 118 A).
In known bus systems of this type, for example, the main microprocessor of a control unit that is a bus subscriber, outputs a transmit instruction to the bus controller for the output of the data filed in the transmit memory after first giving a command to transmit defined data into the transmit memory. No check of the data content currently stored in the transmit memory (for example, with respect to its validity and current status), has taken place. Although bus systems are known which, together with useful data, additionally send a counter reading or so-called xe2x80x9ctoggle bitsxe2x80x9d in order to detect the current status of the data, additional memory space is required for this purpose. A comparable problem exists concerning the data content of the receive memories.
It is an object of the invention to prevent in a simple and cost-effective manner the transmission and receipt of apparently valid data by way of a bus.
This and other objects and advantages are achieved by the control method and apparatus according to the invention, in which after each output and/or read-in of stored data, the data content of the transmit memory and/or of the receive memory is reset to a defined status in the form of a xe2x80x9cresettingxe2x80x9d before the main microprocessor outputs and/or reads in new data. This xe2x80x9cresettingxe2x80x9d takes place, for example, by assigning a defined xe2x80x9cinvalidity labelingxe2x80x9d to the memory content. The resetting of the data content takes place either by the main microprocessor (preferably by means of software) or by the usually simpler bus controller (preferably by means of hardware). In particular, the reset must be carried out before a new transmit or receive instruction is output by the main microprocessor.
Should the data not have been updated (for example, because of a defective path or a defective memory), during the next transmit or receive instruction either the data content is automatically transmitted corresponding to the defined status of the transmit or receive memory (so that the receivers of the data recognize that no valid data are present), or the output or reading-in of the data is prevented completely.
After resetting, preferably, for example, the main microprocessor checks whether the data content does in fact correspond to the defined status. (A prerequisite is a basically existing read-back path.) When the defined status does not exist, a defect is detected and preferably stored. In addition, when this defect is present, a future transmit or receive instruction can be prevented.
Before the next output of data from the transmit memory to the bus and/or before the next reading-in of data from the receive memory, a check can be made whether the defined status (xe2x80x9cinvalidity labelingxe2x80x9d ) is present. If so, output and/or reading-in of data is preferably prevented.
By virtue of the invention, no additional memory location in the area of the useful data is required for protecting the data, and resetting of the data takes place automatically independently of the application of the data.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.